The present invention relates to a semiconductor device with a MIS capacitor and a method of manufacturing the same.
Along with the trend for higher packing density of semiconductor ICs, requirements for miniaturizing of various components have become stricter. Among these various requirements it becomes difficult in obtaining a predetermined capacitance for a capacitor used together with a semiconductor element when the size of the capacitor is decreased. The size of the capacitor presents a restriction to further miniaturization of a semiconductor memory with capacitors. In order to resolve this problem, a conventional semiconductor device is proposed as shown in FIG. 1. A straight trench 13 having a width of 0.4 to 1.0 .mu.m and a length of 0.5 to 5 .mu.m is formed in a p-type silicon semiconductor substrate 11. Phosphorus is diffused by using phosphosilicate glass (PSG) in the surface of the substrate 11 to form an n-type layer. Thereafter, a silicon oxide (SiO.sub.2) layer 27 is formed on the substrate 11 to a thickness of 10 to 50 nm to serve as a dielectric insulating layer. A CVD-polysilicon layer 29 serving as an electrode is deposited in the trench to a thickness of 0.3 to 0.7 .mu.m, thereby preparing a depletion type capacitor. A typical example of this arrangement is described in "Depletion Trench Capacitor Technology for Megabit Level MOSDRAM" by MORIE et. al., IEEE ELECTRON DEVICE LETTERS, Vol. Ed. 2-4, No. 11, November 1983, pp. 411-414.
However, in a capacitor of this type, since the silicon oxide layer as the dielectric insulating layer is directly formed by thermal oxidation in a trench of cross-sectionally rectangular shape, the thickness of the silicon oxide layer at the corners, especially at the edges of the trench opening is decreased. As shown in FIG. 1, acute portions 13A and 13B are formed in the silicon substrate and the electrode. When the resultant structure is used as a capacitor, an electric field is concentrated at the thin portions, thereby decreasing the dielectric breakdown voltage of the capacitor.
When the above-mentioned trench is to be formed by a simple and low-cost photolithography technique, it is difficult to decrease the width of the trench to about 1 .mu.m or less. When a trench is formed by the photolithography technique and an electrode layer is to be formed on the dielectric layer formed in the trench and having a predetermined thickness after the trench is formed, the thickness of the electrode layer must be 0.8 .mu.m or more in order to make the surface of the electrode layer flat. However, in order to obtain such an electrode, productivity is degraded even if any one of doped-polysilicon, molybdenum, tungsten and aluminum is used as an electrode material, thus resulting in inconvenience.
When the n-type layer is formed such that phosphorus is diffused from the PSG layer deposited in the trench, a phosphorus concentration contained in the PSG layer, a diffusion temperature and a diffusion time must be controlled so as to obtain desired concentration and thickness of the n-type layer. However, since a plurality of elements are formed on a single chip in LSIs, the undesirable redistribution of doped impurities in other elements during the diffusion operation for forming the n-type layer must be considered, thereby limiting versatility of process design.
In addition, since the n-type layer is formed to extend outward from the trench, the width of the resultant trench capacitor is larger than the designed trench width by twice the width of the n-type layer. The thickness of the n-type layer is normally about 0.2 .mu.m and cannot be neglected for high packing density of elements.